Silicon Design Engineer
I am a Silicon Design Engineer with experience in DDR/LPDDR Memory Controller (UMC) performance optimization at AMD. I developed SystemVerilog-based scripts for performance monitoring, enabling accurate tracking and analysis of memory performance metrics. My current focus is on high-performance memory systems and RTL Design.
Analyzed and quantified the cross-interference between instruction and data address translation in the second-level TLB (STLB). Implemented dynamic and static STLB partitioning schemes to improve second-level TLB utilization and translation efficiency. Designed a phase-based STLB partitioning algorithm that dynamically allocates resources based on the instruction and data translation requirements of each execution phase. Implemented and evaluated the proposed STLB partitioning scheme using the ChampSim architectural simulator. Achieved an average 1.2% IPC improvement and 6% MPKI reduction over the baseline LRU replacement policy through the proposed dynamic set-wise partitioning scheme.
Designed and implemented a 16 × 8 Asynchronous FIFO in Verilog to enable reliable Clock Domain Crossing (CDC) while mitigating metastability issues. Designed a two flip-flop synchronizer and Gray-code-based read/write pointer architecture to ensure safe cross-clock synchronization and prevent skewed sampling of multi-bit signals.
Designed and implemented a 16-bit, 6-stage pipelined RISC processor based on the IITB-RISC ISA, with emphasis on RTL design, microarchitecture development, and pipeline optimization. Developed data forwarding (bypassing) and hazard detection units to efficiently resolve data hazards, minimize pipeline stalls, and improve instruction throughput. Implemented multi-cycle instructions such as Load Multiple (LM) and Store Multiple (SM) using optimized control logic and Finite State Machine (FSM) design. Developed the processor in Verilog HDL following synthesizable RTL and modular design methodologies to ensure scalability and maintainability. Performed functional verification using ModelSim, validating processor correctness across diverse instruction sequences, data dependencies, and corner-case scenarios.
207/2025 – Present
Contributing to performance optimization of the DDR Memory Controller (UMC) by developing automation scripts, improving team efficiency and workflow productivity. Developed SystemVerilog-based scripts for performance monitoring, enabling accurate tracking and analysis of memory performance metrics. Brought up and validated fixed LPDDR5 DRAM timing configurations for high data-rate operation in the memory controller, performed simulation-based verification, and correlated results with SoC timing and performance targets. Performed latency analysis to evaluate the impact of memory encryption on memory access performance. Conducted a comparative performance study of 2-Rank and 4-Rank LPDDR configurations to analyze performance trade-offs, scalability, and bandwidth utilization. Analyzed DDR/LPDDR architecture and DRAM timing parameters (read latency, write latency, and bandwidth), identifying opportunities for memory subsystem performance optimization.
Post Graduation • 2025
9.36
Graduation • 2021
8.96
Interested in collaboration or just want to say hello? Feel free to reach out!